1. Field of the Disclosure
The present disclosure relates generally to processing systems and more particularly to multiple-level memory hierarchies in processing systems.
2. Description of the Related Art
A processing system typically employs a memory hierarchy to store data for use by components of the system. The memory hierarchy includes two or more levels of memory, with the lower-level memories typically being smaller but with faster access, and the higher-level memories being larger but with slower access. As such, a lower-level memory often acts as a cache to temporarily store data from a higher-level memory, thereby allowing requested data to be accessed more quickly when it is present in the cache. However, space and power limitations may limit the size of the cache, which can result in requested data being absent from the cache (that is, a “cache miss”). In such instances, the requested data is then accessed from a slower higher-level memory, which can introduce a performance bottleneck. Moreover, frequent write accesses to higher-level memories can introduce reliability issues as many higher-level memories are implemented using memory architectures that exhibit wear-out as the number of write accesses or program-erase cycles increases.